For a general reference, here [0] (PDF) is a somewhat detailed description (that is, it actually discusses how this particular implementation solves the problems that arise before it) of an out-of-order implementation for a simplistic RISC ISA. Suffice to say, it doesn't really have all that much in common with the classical 5-stage RISC pipeline.
I'm often dismissive of RISC-V posts, but I really loved this one. It does a great job of presenting the material: good graphics, readable text and references at the bottom of the text. I've been focused on smaller CPUs on durt cheap process nodes, but this was great.
[0] https://user.eng.umd.edu/~blj/risc/RiSC-oo.1.pdf