Having worked with people doing bringup of specialized chips, I am awed at how the world has changed.
> When the first chips came back from the foundry in May, the team pointed its internal AI models at designing software to run benchmarks such as SemiAnalysis’s InferenceX. On DeepSeek’s multi-head latent attention kernel benchmark, performance climbed from 0.31 percent of the theoretical ceiling (set by the chip’s compute and memory bandwidth) to 88.94 percent in roughly 40 hours. Ho says this result is repeatable, so the time between when foundries deliver the first chips and when production ramps up can be reduced. “All our schedule assumptions are going to be based on the fact we have this capability now,” he says.
Production grade CPU design is more than just the RTL (the source code.) To achieve the performance numbers that these companies get, you have to do a ton of optimization in your physical design to achieve the power/performance/area (PPA) metrics that make these products competitive. LLMs are not suitable for that kind of work.
There are people working on PPA optimization and trying to shake up how things are done, just not with LLMs.
Something that I think is fascinating, though, is that labs are no longer beholden to the limitations of commercial design software. Want to replace your simulator and optimizer with a fully custom verifiable stack of Lean proofs of optimality and correctness? Just throw your unlimited token budget at it.
I mean you can design anything without a license. Selling it is where the problems come up. Even then there are likely places in China that would still make it for you.
> When the first chips came back from the foundry in May, the team pointed its internal AI models at designing software to run benchmarks such as SemiAnalysis’s InferenceX. On DeepSeek’s multi-head latent attention kernel benchmark, performance climbed from 0.31 percent of the theoretical ceiling (set by the chip’s compute and memory bandwidth) to 88.94 percent in roughly 40 hours. Ho says this result is repeatable, so the time between when foundries deliver the first chips and when production ramps up can be reduced. “All our schedule assumptions are going to be based on the fact we have this capability now,” he says.
Like, why couldn't they invent a new word and not hijack an existing word?
It's jalapeño grill would you say?
There are people working on PPA optimization and trying to shake up how things are done, just not with LLMs.
The value lies in the design space exploration, which is what an LLM can easily do.
https://en.wikipedia.org/wiki/Design_space_exploration
Except the problem is not restricted to the actual ISA or its HDL implementation, etc.
It's even just getting space / time in a fab at that advanced of a process node.